The total resistance of a power MOSFET when it is turned on is generally the sum of the resistances of the metal conductors (bonding wires, buses, etc.) and the channel resistance. The performance of power MOSFETs fabricated as integrated circuits (ICs) has suffered in comparison with the performance of their discrete counterparts because of the resistance of the metal conductors. This problem was overcome temporarily by the introduction of dual-layer metallization into power ICs. More recently, however, further reductions in the channel resistance of vertical and lateral power MOSFETs have once again focused attention on the resistance of the metal interconnects. In some cases, for example, where cross-chip busing is required, the metal resistance can exceed the resistance of the silicon devices.
In a conventional IC power MOSFET, the metal layers are deposited by sputtering, chemical vapor deposition, or evaporation and are overlain by a passivation layer which is typically formed of silicon nitride or some type of glass (e.g., borophosphosilicate glass). Increasing the thickness of metal layers so fabricated to minimize their contribution to resistance is in many ways incompatible with the desire for increased packing density within the IC. Moreover, even at a thickness of 1 .mu.m, a sheet resistance of 30 m.OMEGA./square can present a significant problem in the design of a 50 m.OMEGA. lateral power MOSFET. As operating voltages decline from 12 V to 5 V, and even to 3 V, the size of the individual device cells has been reduced. In a closed-cell array of alternating source and drain cells, for example, which is currently the preferred structure, reducing the size of the cells forces the first metal layer to a tighter pitch and smaller contacts. In some embodiments, this pitch requirement reduces the thickness of the first metal layer to 1 .mu.m or below, even as low as 0.3 .mu.m. Moreover, a thick first metal layer may complicate the planarization process needed to avoid step coverage problems in the second metal layer.
Increasing the thickness of the second metal layer also presents problems, particularly in the etching process. Beyond a thickness of 2 .mu.m, dry etching becomes difficult due to the need for a thick photoresist and due to complexities in the metal etch process itself (i.e., redeposition of etched materials, changes in gas stoichiometry, heating, etc.). Wet etching suffers from lift off of the resist, which leads to notching ("mouse biting") and requires very large metal-to-metal spacing (for example, 15 .mu.m for a 4 .mu.m thick metal layer) and a large metal overlap of vias. A metal layer meeting these requirements is useless in the logic areas of the IC, because the minimum line widths and spacing permitted yield too large a pitch and too few interconnects per unit area to allow for dense packing of logic.
Metal resistance impacts two areas of power IC design in particular: (i) the buses between devices and along the edge of the die, and (ii) the conductive fingers within a given lateral power device. In the buses between devices the metal acts as a series resistance element. Its contribution to total resistance can be calculated by the number of squares times its sheet resistance. Consider, for example, the three-phase push-pull motor driver shown in FIG. 1A. The drive consists of six transistors, three high-side and three low-side. All three low-side MOSFETs A.sub.LSS, B.sub.LSS, and C.sub.LSS must have a low resistance connection to the ground pad of the IC. Likewise, all three high-side devices, A.sub.HSS, B.sub.HSS, and C.sub.HSS must share a common low-resistance bus to a V.sub.DD pad. Each phase has an output pad (A.sub.out, B.sub.out and C.sub.out) located schematically at the common node between the high-side and low-side MOSFET. Thus, at least five power pads are required. Unfortunately, the output pads cannot be located in the center of the die, as shown in FIG. 1B. "Deep" bond wires, i.e., bond wires which extend from the edge of the die (where the leadframe is located) to the center of the die are generally forbidden. The risk of a "deep" bond wire shorting to the surface of the die or to another bond wire is too great. Another risk is sagging of the wire where it touches the "scribe street" causing a short to ground (a failure referred to as "wire wash"). In thin profile surface-mount packages, a deep bond wire may even protrude through the top of the plastic package. Moreover, a single bond wire may exhibit a resistance of over 50 m.OMEGA.. For these and other reasons, the bond pads in an IC must generally be located near the edge of the die.
Continuing the example, rearranging the push-pull stages to place the output pads near the edge of the die, as shown in FIG. 1C, further lengthens the ground and V.sub.DD bus lines, thereby increasing their resistance. The net result is that no layout satisfies the need for low-resistance V.sub.DD, ground and output connections without increasing the number of power-related pads from five to at least seven.
The resistive contributions of the metal within a device are even more complex. FIG. 2A illustrates an idealized model cf a MOSFET M having a bond wire resistance R.sub.wire, a lumped metal finger resistance R.sub.metal and a MOSFET channel resistance. The assumption that the finger resistance can be "lumped" is disproved by reference to FIG. 2B, which shows MOSFETs M.sub.A -M.sub.F connected in parallel between a drain finger D and a source finger S. Drain finger D contains five squares designated 1d-5d, and source finger S contains five squares designated 1s-5s.
Assume for the moment that MOSFETs M.sub.A -M.sub.F all carry the same current. Notice that, on the source side, the metal square labeled 5s must conduct the current of all six MOSFETs. Square 5d on the drain side carries only the current of MOSFET M.sub.F. Instead, the square labeled 1d must handle all of the current. Since more current is flowing in square 1d on the drain side and square 5s on the source side, the voltage drop in these squares is higher than in the other squares. The equivalent circuit is shown in FIG. 2C, wherein the distributed resistances represented by squares 1d-5d and 1s-5s are shown between the individual MOSFETs. Because of this distributed resistance, the MOSFETs cannot be considered in parallel nor can the current through them be considered uniform. The net result is that the equivalent resistance of the network can be higher than the model of the simple lumped resistance of the metal finger added to the parallel resistances of the MOSFETS.
FIG. 3A illustrates the voltage drop along source finger S (V.sub.source) and drain finger D (V.sub.drain) when a known current I is forced through the network. As expected, most of the voltage drop occurs at one end of source finger S and at the other end of the drain finger D. The voltage along each finger varies parabolically as more MOSFETs feed current into the finger. Given the nonlinear variation of V.sub.source and V.sub.drain, the voltage across any given MOSFET is the difference between the drain and source finger potentials at that point (V.sub.drain -V.sub.source). Note that, at the two ends, the voltage across the MOSFETs (M.sub.A and M.sub.F) is a relatively large percentage of the terminal potential (V.sub.DD). Halfway down the fingers, however, the voltage drops along each finger become significant, and the voltage across the central MOSFETs (M.sub.C and M.sub.D) falls to a minimum. If we assume that the current density is low enough to prevent saturation in any MOSFET, then each MOSFET can be considered as a linear resistance. The current through any given MOSFET is then V.sub.ds /R.sub.ds, wherein V.sub.ds is the voltage across the particular MOSFET and R.sub.ds is the resistance of the MOSFET.
The curve C.sub.1 of FIG. 3B illustrates the voltage V.sub.ds across each of MOSFETs M.sub.A -M.sub.F. It is clear from FIG. 3B that MOSFETs M.sub.C and M.sub.D at the center of the fingers carry less current than those at the ends. Because they conduct a smaller percentage of the total current, these MOSFETs behave as if they have a higher resistance than the MOSFETs located towards the ends of the fingers. Making a finger even longer adds even more cells to the center that do not carry much current, so the equivalent resistance for a given area of the die increases. As a result, without including any effects due to the gate bias or current saturation or the MOSFETs, the influence of metal finger resistance is to increase the total device resistance nonlinearly with increasing finger length. FIGS. 3B also shows the voltage drop that would prevail across each of MOSFETs M.sub.A -M.sub.F in the ideal model with no parasitic resistance (curve C.sub.3) and in the lumped resistance model illustrated in FIG. 2A (curve C.sub.2).
As the voltage between the gate and source pads is increased by external circuit conditions, the devices at the ends of the fingers go into current saturation first, placing an increased conduction burden on the cells along the center of the fingers. The latter cells then go into saturation sooner than they would otherwise, and the effect cascades. This phenomenon points up the second problem with finger resistance, i.e., the non-uniform current leads to premature saturation of the individual MOSFETs, a smaller region of linear operation, and a non-uniform distribution of power along the metal fingers S and D.
In addition, the distributed resistance along finger S increases the voltage at the end of the finger (MOSFET M.sub.A) and therefore reduces the level of gate drive. The farther away the device is from the gate pad, the larger the reduction on gate drive. A lower gate drive voltage (V.sub.gs) means that the MOSFET will have a higher resistance and saturate sooner.
In the prior art, triangular or wedge-shaped buses have been used to avoid electromigration (a reliability problem resulting from high current densities in a soft metal such as aluminum). This tends to equalize the voltage drops between the MOSFETs along a given bus or finger (i.e., the cross-sectional area of the bus increases in the direction of the pad), but the restrictions imposed on the layout by triangular buses are incompatible with today's high-density device technology. Moreover, as the interdigitated bus arrangement shown in FIG. 4 indicates, the bus resistance problem is two-dimensional: not only does the metal contribute to resistance along a finger (perpendicular to the die edge), but it also adds a distributed effect in the metal source bus and drain bus along the edge of the die. Any attempt to make triangles out of the bus would result in a waste of area having consequences worse than the distributed resistance problem that it was intended to overcome.
FIG. 5A illustrates an array of tightly packed device cells built into a rectilinear grid. Some of the advantages of this pattern are discussed in U.S. Pat. No. 5,412,239, incorporated herein by reference. The polysilicon gate is fabricated in a "cookie cutter" geometry, i.e., a sheet with a rectilinear array of openings, the source contacts and drain contacts extending through the openings (labeled S for source, D for drain) in an alternating fashion. As shown in FIG. 5B, the traces of the first metal layer are arranged in a diagonal pattern to connect with all contacts of like type (drain or source). Again S designates a source metal trace; D designates a drain metal trace. Then, as shown in FIG. 5C, the second metal layer includes interdigitated fingers which are arranged in a pattern parallel to the cells such that alternating fingers are connected through vias to the underlying source and drain cells. In other words, via connections between the first and second metal layers occur in alternating "stripes". Under a drain stripe, only vias to "drain" first metal buses are included. (This is shown as the central region in FIG. 5B.) Current in first metal layer source buses in this region must flow laterally to the nearest via under a second metal layer source bus.
What is needed, then, is a means to conduct high currents in an IC power device at low values of laterally distributed resistance. The technique should place minimum restrictions on the geometric patterns of the polysilicon gate and first metal layer so as to allow them to be optimized for achieving the minimum device resistance in a given area. Furthermore, extremely thick passivated metal must be avoided to prevent cracking of the passivant over metal steps. Such cracks may create reliability problems.